1. Field of the Invention
The present invention relates to a reference voltage driving circuit. More particularly, the present invention relates to a reference voltage driving circuit and a pipelined analog to digital converter including the reference voltage driving circuit configured to allow a reference voltage supplied to MDAC (Multiplying Digital to Analog Converter) and a flash ADC (Analog to Digital Converter) of pipelined ADC to hold a constant value so that a high speed analog to digital conversion can be stably implemented without using a large capacity on-chip capacitor.
2. Description of the Related Art
Recently, high speed/high resolution ADCs are widely employed in a variety of electronic systems including computer modems, next generation wireless telephones, satellite receivers, process control systems, high speed digital communication networks and medical equipment thanks to development of Complementary Metal Oxide Semiconductor (CMOS) process and digital signal process technologies. Particularly, application systems such as Thin Film Transistor-Liquid Crystal Displays (TFT-LCDs) and CDMA (Code Division Multiple Access) system wireless communication standard IMT-2000, and xDSL (x Digital Subscriber Line) require sampling speed of over 100 MHz and resolutions of over 8 bits, thereby necessitating use of high speed/high resolution ADCs.
The ADCs used for these types of high performance systems require minimum external pins, small areas and low power consumptions.
FIG. 1 is a block diagram illustrating a construction of a pipelined ADC employed for high speed/high resolution analog-to-digital conversion.
Referring to FIG. 1, the ADC structured of plural stages includes a sample/holder amplifier (11-1) for receiving an analog input signal from a preceding stage thereof and sampling/holding the signal, a flash ADC (12-1 to 12-n) for converting the analog signal sampled by the sample/holder amplifier (11-1) to a digital output signal, and an MDAC (Multiplying DAC) for converting the digital signal outputted from the flash ADC (12-1 to 12-n) again to an analog signal, summing up the analog signal with an analog signal of the preceding stage having passed the sample/holder amplifier (11-1) and outputting the summed signal.
A DCL (Digital Correction Logic.14) processes a digital signal converted at each stage of the flash ADC (12-1 to 12-n) and outputs a final digital signal.
Meanwhile, a reference voltage driving circuit 10 of the ADC as illustrated in FIG. 1 supplies two reference voltages for converting an analog signal to a digital signal. The ADC divides a gap between the two reference voltages into predetermined numbers of levels, compares the inputted analog signal with the divided levels and digitalizes by mapping to the divided level.
The two reference voltages REFT and REFC are processed by the reference voltage driving circuit 10 and are supplied to each MDAC (11-2 to 11-n) and each flash ADC (12-1 to 12-n).
The reference voltage driving circuit 10 is operated in such a manner that an inner transistor switches between turn-on and turn-off according to a clock signal, and instant charge and discharge of channel charges are repeated. Because of this operation, an output node voltage of the reference voltage driving circuit 10 is hard to hold a constant value. Consequently, as long as the reference voltage is not held at a constant level, it is difficult to expect an operational speed and a resolution required by a high speed/high resolution ADC.
In order to cope with the aforementioned problem, the existing reference voltage driving circuit is so constituted as to bypass a noise component generated from high frequency by connecting capacities of several F at an external side of chips of an integrated circuit. However, this kind of method cannot be applied for use on SoC (System on Chip) where too many limitations are involved with pins.
FIG. 2 is an exemplary circuit diagram illustrating the conventional reference voltage driving circuit for restraining the use of external pins. The reference voltage driving circuit 10 in FIG. 2 includes amplifiers 21 and 22 each having a unity gain. Output terminals of the amplifiers 21 and 22 are connected to large capacity capacitors 23 and 24 and integrated in order to remove noise components created by the high frequency. In this case, each of the large capacity capacitors has a very large size. After all, area of the ADC is enlarged in order not to use external pins if the large capacity of capacitors is employed thereinside.
Particularly, this kind of inner capacitors require a further enlarged capacitance as an operational speed of the ADC increases. Consequently, in case of an ADC having an operational speed of over 100 MHz, an area of the inner capacitor further increases to pose as a considerably cumbersome burden.